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Integrated Circuit Systems, Inc.
ICS951702
Advance Information
PIIITM System Clock Chip for DDR SDRAM
Recommended Application: 1644 and 1644T applications using DDR Output Features: * 7 - Differential pairs DDR SDRAM clocks * 3 - CPU @ 2.5V (1 - Free running) * 8 - PCI @ 3.3V (1 - Free running and 1 - 2 X optional) * 2 - AGP @ 3.3V * 1 - IOAPIC @ 2.5V * 1 - 48MHz, @3.3V * 1 - REF @ 3.3V Features: * Up to 147MHz frequency support * Power management through PD# * Spread spectrum for EMI control (0 to -0.5% down spread, 0.25% center spread). * Uses external 14.318MHz crystal Skew Specifications: * CPU - CPU: <250ps * PCI - PCI: <500ps * SDRAM - SDRAM: <250ps * AGP - AGP: <250ps * PCI - AGP: <750ps * CPU - SDRAM: <750ps * CPU - PCI: <3ns
VDDL IOAPIC GND X1 X2 AVDD **FS0/REF VDD **FS1/AGP0 AGP1 GND **FS2/PCI_F PCICLK0 PCICLK1 PCICLK2 GND VDD PCICLK3 PCICLK4 PCICLK5 GND VDD 1 PCICLK6 *PCI_STOP# *CPU_STOP# *Vtt_PWRGD/PD# VDD **FS3/48MHz
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDL CPUCLK_F CPUCLK0 CPUCLK1 GND DDRT0 DDRC0 GND VDDL DDRT1 DDRC1 DDRT2 DDRC2 VDDL GND DDRT3 DDRC3 DDRT4 DDRC4 GND VDDL DDRT5 DDRC5 DDRT6 DDRC6 SCLK SDATA GND
56-Pin 240 mil TSSOP
Notes: * Internal Pull-up Resistor of 120K to VDD ** Internal Pull-down of 120K to GND 1. PCICLK6 is selectable 2X via I2C
Block Diagram
PLL2 48MHz
Functionality
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU SDRAM 66.66 66.66 66.66 100.00 100.00 66.66 100.00 100.00 100.00 133.33 133.33 66.66 133.33 100.00 133.33 133.33 66.66 66.66 66.66 100.00 100.00 66.66 100.00 100.00 100.00 133.33 133.33 66.66 133.33 100.00 133.33 133.33
X1 X2
XTAL OSC PLL1 Spread Spectrum
REF0 IOAPIC
CPU DIVDER Stop
2
CPUCLK (1:0) CPUCLK_F
SDRAM DIVDER
7
DDRC (6:0) DDRT (6:0) PCICLK (6:0) PCICLK_F
Vtt_PWRGD/PD# MODE SDATA SCLK FS (3:0)
Control Logic Config. Reg.
AGP DIVDER PCI DIVDER Stop
7
5
2
AGP (1:0)
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Note: PCICLK = 33.33MHz AGP = 66.66MHz
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS951702
ICS951702
Advance Information
Pin Descriptions
PIN NUMBER 1, 36, 43, 48, 56 2 3, 11, 16, 21, 29, 37, 42, 49, 52 4 5 6 7 8, 17, 22, 27 9 10 12 20, 19, 18, 15, 14, 13 23 24 PIN NAME VDDL IOAPIC GND X1 X2 AVDD FS02, 3 REF0 VDD FS12, 3 AGP0 AGP1 PCICLK_F FS21, 2 PCICLK (5:0) PCICLK6 PCI_STOP# TYPE PWR OUT PWR IN OUT PWR IN OUT PWR IN OUT OUT OUT IN OUT OUT IN DESCRIPTION Power supply pins, nominal 2.5V 2.5V clock outputs Ground pins Crystal input,nominally 14.318MHz. Crystal output, nominally 14.318MHz. Analog power supply for 3.3V Frequency select pin. 14.318 MHz reference clock. Power supply pins, nominal 3.3V Frequency select pin. AGP outputs defined as 2X PCI. AGP output defined as 2X PCI. Free running PCI clock Frequency select pin. PCI clock outputs. PCI clock output (selectable 1X or 2X via I2C) Stops all PCICLKs at logic 0 level, when input low besides the PCICLK_F clocks which are controllable by I2C bits whether they are free running or stopped by PCI_STOP. Stops all CPUCLKs at logic 0 level, when input low. The individual CPU clocks are controllable by I2C bits whether they are free running or stopped by CPU_STOP. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal. When Vtt_PWRGD goes high the frequency select will be latched at power on thereafter the pin is an asynchronous active low power down pin. Frequency select pin 48MHz output clock Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant "True" clocks of differential pair DDR SDRAM outputs - 2.5V "Complementry" clocks of differential pair DDR SDRAM outputs - 2.5V 2.5V CPU clocks Free running CPU clock. Not affected by the CPU_STOP#.
25
CPU_STOP#
IN
PD# 26 Vtt_PWRGD FS32, 3 48MHz SDATA SCLK DDRT (6:0) DDRC (6:0) CPUCLK (1:0) CPUCLK_F
IN
IN IN OUT I/O IN OUT OUT OUT OUT
28 30 31 33, 35, 39, 41, 45, 47, 51 32, 34, 38, 40, 44, 46, 50 53, 54 55
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Internal pull-down resistor of 120K to GND on indicated inputs. 3: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS951702
Advance Information
General Description
The ICS951702 is a main clock synthesizer chip for PIII based systems with ALI 1644 style chipset. This provides all clocks required for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS951702 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
STATE 0 1 Pin 24 PCI_STOP# (Input) PCICLK4 (Output, Active) Pin 25 CPU_STOP# (Input) CPUCLKs (Output, Active) Pin 26 PD# (Input) Active
Power Groups
AVDD = PLL Core & Xtal VDD48 = 48MHz, PLL2 VDDL, VDD = Digital
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ICS951702
Advance Information
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit Description Spread Precentage +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread PWD
FS3 FS2 FS1 FS0 CPUCLK SDRAM PCICLK AGP (MHz) (MHz) (MHz) (MHz) Bit2 Bit7 Bit6 Bit5 Bit4 0 0 0 0 0 66.66 66.66 33.33 66.66 0 0 0 0 1 66.66 100.00 33.33 66.66 0 0 0 1 0 100.00 66.66 33.33 66.66 0 0 0 1 1 100.00 100.00 33.33 66.66 0 0 1 0 0 100.00 133.33 33.33 66.66 0 0 1 0 1 133.33 66.66 33.33 66.66 0 0 1 1 0 133.33 100.00 33.33 66.66 0 0 1 1 1 133.33 133.33 33.33 66.66 0 1 0 0 0 66.66 66.66 33.33 66.66 0 1 0 0 1 66.66 100.00 33.33 66.66 0 1 0 1 0 100.00 66.66 33.33 66.66 0 1 0 1 1 100.00 100.00 33.33 66.66 0 1 1 0 0 100.00 133.33 33.33 66.66 0 1 1 0 1 133.33 66.66 33.33 66.66 0 1 1 1 0 133.33 100.00 33.33 66.66 Bit 2, Bit 7:4 0 1 1 1 1 133.33 133.33 33.33 66.66 1 0 0 0 0 69.99 69.99 35.00 69.99 1 0 0 0 1 69.99 105.00 35.00 69.99 1 0 0 1 0 105.00 69.99 35.00 69.99 1 0 0 1 1 105.00 105.00 35.00 69.99 1 0 1 0 0 105.00 140.00 35.00 69.99 1 0 1 0 1 140.00 69.99 35.00 69.99 1 0 1 1 0 140.00 105.00 35.00 69.99 1 0 1 1 1 140.00 140.00 35.00 69.99 1 1 0 0 0 73.33 73.33 36.66 73.33 1 1 0 0 1 73.33 110.00 36.66 73.33 1 1 0 1 0 110.00 73.33 36.66 73.33 1 1 0 1 1 110.00 110.00 36.66 73.33 1 1 1 0 0 110.00 146.66 36.66 73.33 1 1 1 0 1 146.66 73.33 36.66 73.33 1 1 1 1 0 146.66 110.00 36.66 73.33 1 1 1 1 1 146.66 146.66 36.66 73.33 0 - Frequency is selected by hardware select, Latched Inputs Bit 3 1 - Frequency is selected by Bit 2, 7:4 0 - Normal Bit 1 1 - Spread Spectrum Enabled 0 Ru ing Bit 0 1- -Tristnne all outputs at
00000 Note1
0 0 0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. The I2C readback of the power up default indicates the revision ID in bits 2, 7:4 as shown.
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ICS951702
Advance Information
Byte 1: Active/Inactive Register (1= enable, 0 = disable)
Byte 2: Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
10 9 28 2 55 54 53 X 1 1 1 1 1 1 1 FS3# AGP1 AGP0
DESCRIPTION
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
13 14 15 18 19 51, 50 47, 46 45, 44 1 1 1 1 1 1 1 1
DESCRIPTION
PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 SDRAMT0, SDRAMC0 SDRAMT1, SDRAMC1 SDRAMT2, SDRAMC2
48MHz IOAPIC CPUCLK_F CPUCLK0 CPUCLK1
Byte 3: Active/Inactive Register (1= enable, 0 = disable)
Byte 4: Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
12 39, 38 35, 34 33, 32
PWD
X X X 1 1 1 1 1 FS0# FS1# FS2#
DESCRIPTION
PIN# PWD
20 23 23 33, 32 1 1 1 1 1 1 1 1
DESCRIPTION
Reser ved PCICLK5 PCICLK6 PCICLK6; 1=1X, 0=2X Reser ved Reser ved Reser ved SDRAMT6, SDRAMC6
PCICLK_F Reserved SDRAMT3, SDRAMC3 SDRAMT4, SDRAMC4 SDRAMT5, SDRAMC5
Byte 5: Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
1 1 1 1 1 1 1 1
DESCRIPTION
Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
0 0 0 0 0 1 1 1
DESCRIPTION
Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved
Notes:
Note: Don't write into this register, writing into this register can cause malfunction
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
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ICS951702
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3V, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Input frequency Input Capacitance1 Clk Stabilization1
1
SYMBOL V IH VIL IIH IIL1 IIL2 IDD3.3OP66 IDD3.3OP100 Fi CIN CINX TSTAB
CONDITIONS
MIN TYP 2 VSS-0.3 -5 -200
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 100MHz VDD = 3.3 V; Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq.
12 27
MAX UNITS V DD+0.3 V 0.8 V 5 mA mA mA 77 mA 100 16 MHz 5 45 3 pF pF ms
Guaranteed by design, not 100% tested in production.
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ICS951702
Advance Information
Electrical Characteristics - CPUCLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew SYMBOL VOH2B VOL2B I OH2B IOL2B tr2B tf2B
1 1
CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, V OL = 0.4 V VT = 1.25 V VT = 1.25 V
MIN 2
TYP
19
MAX UNITS V 0.4 V -19 mA mA 1.6 1.6 ns ns % ps ps ps
dt2B1 tsk2B1
45
55 250 250 150
Jitter, Cycle-to-cycle t jcyc-cyc2B1 VT = 1.25 V VT = 1.25 V tj1s2B1 Jitter, One Sigma
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time Skew1
1 1
SYMBOL VOH1 VOL1 IOH1 I OL1 tr1 tf1 dt1 tsk1
CONDITIONS I OH = -11 mA I OL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
25
MAX UNITS V 0.4 V -22 mA mA 2 2 ns ns % ps ps ps ps
Duty Cycle
45
55 500 250 150
Jitter, Cycle-to-cycle tjcyc-cyc2B1 VT = 1.5 V Jitter, One Sigma1 t j1s1 VT = 1.5 V 1 Jitter, Absolute t jabs1 VT = 1.5 V
1
-500
500
Guaranteed by design, not 100% tested in production.
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7
ICS951702
Advance Information
Electrical Characteristics - SDRAMT & C
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew SYMBOL VOH2B VOL2B IOH2B I OL2B t r2B1 t f2B1 dt2B1 t sk2B1 CONDITIONS I OH = -12.0 mA I OL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V 47 MIN 2 TYP MAX UNITS V 0.4 V -19 mA mA 1.6 1.6 53 250 250 150 ns ns % ps ps ps
19
Jitter, Cycle-to-cycle t jcyc-cyc2B1 VT = 1.25 V t j1s2B1 VT = 1.25 V Jitter, One Sigma
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1 1
SYMBOL V OH4B V OL4B IOH4B IOL4B Tr4B Tf4B Dt4B Tj1s4B Tjabs4B
CONDITIONS IOH = -12 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
TYP
19
MAX UNITS V 0.4 V -19 mA mA 2 2 ns ns % ns ns
Duty Cycle
45 -1
55 0.5 1
Jitter, One Sigma Jitter, Absolute1
1
Guaranteed by design, not 100% tested in production.
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8
ICS951702
Advance Information
Electrical Characteristics - 24MHz, 48MHz, REF
TA = 0 - 70 C; V DD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle1 Jitter, One Sigma Jitter, Absolute1
1 1
SYMBOL VOH5 VOL5 IOH5 I OL5 tr5 tf5 dt5 t j1s5 tjabs5
CONDITIONS IOH = -16 mA IOL = 9 mA V OH = 2.0 V V OL = 0.8 V V OL = 0.4 V, V OH = 2.4 V V OH = 2.4 V, V OL = 0.4 V V T = 1.5 V V T = 1.5 V V T = 1.5 V
MIN 2.4
TYP
16
MAX UNITS V 0.4 V -22 mA mA 2 2 ns ns % ns ns
45 -1
55 0.5 1
Guaranteed by design, not 100% tested in production.
0664--07/29/02
9
ICS951702
Advance Information
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controlle r (Host) Start Bit Address D2(H ) Dummy Command Code A CK Dummy Byte Count A CK Byte 0 A CK Byte 1 A CK Byte 2 A CK Byte 3 A CK Byte 4 A CK Byte 5 A CK Byte 6 A CK Byte 7 A CK Stop Bit ICS (Sla ve/Re ceiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controlle r (Host) Start Bit Address D3(H ) ICS (Sla ve/Re ceiver)
A CK
ACK
A CK Byte Count Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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10
ICS951702
Advance Information
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248174 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS951702
Advance Information
N
c
L
INDEX AREA
E1
E
12 D
a
6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 aaa -0.10 -.004 VARIATIONS N D mm. MIN 13.90 MAX 14.10 MIN .547 D (inch) MAX .555
A2 A1
A
-Ce
b SEATING PLANE
56
10-0039
Reference Doc.: JEDEC Publication 95, MO-153
aaa C
Ordering Information
ICS951702yG-T
Example:
ICS XXXXXX y G - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS = Standard Device
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